Datasheet

41.8.5 SPI Status Register
Name: SPI_SR
Offset: 0x10
Reset: 0x00000000
Property: Read-only
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
SPIENS
Access
R
Reset 0
Bit 15 14 13 12 11 10 9 8
SFERR UNDES TXEMPTY NSSR
Access
R R R R
Reset 0 0 0 0
Bit 7 6 5 4 3 2 1 0
OVRES MODF TDRE RDRF
Access
R R R R
Reset 0 0 0 0
Bit 16 – SPIENS SPI Enable Status
Value Description
0
SPI is disabled.
1
SPI is enabled.
Bit 12 – SFERR Slave Frame Error (cleared on read)
Value Description
0
There is no frame error detected for a slave access since the last read of SPI_SR.
1
In Slave mode, the Chip Select raised while the character defined in SPI_CSR0.BITS was not
complete.
Bit 10 – UNDES Underrun Error Status (Slave mode only) (cleared on read)
Value Description
0
No underrun has been detected since the last read of SPI_SR.
1
A transfer starts whereas no data has been loaded in SPI_TDR.
Bit 9 – TXEMPTY T
ransmission Registers Empty (cleared by writing SPI_TDR)
Value Description
0
As soon as data is written in SPI_TDR.
1
SPI_TDR and internal shift register are empty. If a transfer delay has been defined, TXEMPTY is set
after the end of this delay
.
Bit 8 – NSSR NSS Rising (cleared on read)
Value Description
0
No rising edge detected on NSS pin since the last read of SPI_SR.
1
A rising edge occurred on NSS pin since the last read of SPI_SR.
SAM E70/S70/V70/V71 Family
Serial Peripheral Interface (SPI)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 996