Datasheet

41.8.4 SPI Transmit Data Register
Name: SPI_TDR
Offset: 0x0C
Reset: –
Property: Write-only
Bit 31 30 29 28 27 26 25 24
LASTXFER
Access
W
Reset –
Bit 23 22 21 20 19 18 17 16
PCS[3:0]
Access
W W W W
Reset – – – –
Bit 15 14 13 12 11 10 9 8
TD[15:8]
Access
W W W W W W W W
Reset – – – – – – – –
Bit 7 6 5 4 3 2 1 0
TD[7:0]
Access
W W W W W W W W
Reset – – – – – – – –
Bit 24 – LASTXFER Last T
ransfer
This field is only used if variable peripheral select is active (SPI_MR.PS = 1).
Value Description
0
No effect
1
The current NPCS is deasserted after the transfer of the character written in TD. When
SPI_CSRx.CSAA
T is set, the communication with the current serial peripheral can be closed by raising
the corresponding NPCS line as soon as TD transfer is completed.
Bits 19:16 – PCS[3:0] Peripheral Chip Select
This field is only used if variable peripheral select is active (SPI_MR.PS = 1).
If SPI_MR.PCSDEC = 0:
PCS = xxx0 NPCS[3:0] = 1
110
PCS = xx01 NPCS[3:0] = 1101
PCS = x011 NPCS[3:0] = 1011
PCS = 0111 NPCS[3:0] = 0111
PCS = 1111 forbidden (no peripheral is selected)
(x = don’t care)
If SPI_MR.PCSDEC = 1:
NPCS[3:0] output signals = PCS.
Bits 15:0 – TD[15:0] Transmit Data
Data to be transmitted by the SPI interface is stored in this register. Information to be transmitted must be written to
this register in a right-justified format.
SAM E70/S70/V70/V71 Family
Serial Peripheral Interface (SPI)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 995