Datasheet

41.8.3 SPI Receive Data Register
Name: SPI_RDR
Offset: 0x08
Reset: 0x0
Property: Read-only
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
PCS[3:0]
Access
R R R R
Reset 0 0 0 0
Bit 15 14 13 12 11 10 9 8
RD[15:8]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RD[7:0]
Access
R R R R R R R R
Reset 0 0 0 0 0 0 0 0
Bits 19:16 – PCS[3:0] Peripheral Chip Select
In Master mode only
, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits
are read as zero.
When using Variable Peripheral Select mode (PS = 1 in SPI_MR), it is mandatory to set SPI_MR.WDRBT bit if the
PCS field must be processed in SPI_RDR.
Bits 15:0 – RD[15:0] Receive Data
Data received by the SPI Interface is stored in this register in a right-justified format. Unused bits are read as zero.
SAM E70/S70/V70/V71 Family
Serial Peripheral Interface (SPI)
©
2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 994