Datasheet

Value Description
0
No Effect. In Master mode, a transfer can be initiated regardless of SPI_RDR state.
1
In Master mode, a transfer can start only if SPI_RDR is empty, i.e., does not contain any unread data.
This mode prevents overrun error in reception.
Bit 4 – MODFDIS Mode Fault Detection
Value Description
0
Mode fault detection enabled
1
Mode fault detection disabled
Bit 2 – PCSDEC Chip Select Decode
When PCSDEC = 1, up to 15 chip select signals can be generated with the
four NPCS lines using an external 4-bit to
16-bit decoder. The chip select registers define the characteristics of the 15 chip selects, with the following rules:
SPI_CSR0 defines peripheral chip select signals 0 to 3.
SPI_CSR1 defines peripheral chip select signals 4 to 7.
SPI_CSR2 defines peripheral chip select signals 8 to 11.
SPI_CSR3 defines peripheral chip select signals 12 to 14.
Value Description
0
The chip select lines are directly connected to a peripheral device.
1
The four NPCS chip select lines are connected to a 4-bit to 16-bit decoder.
Bit 1 – PS Peripheral Select
Value Description
0
Fixed Peripheral Select
1
Variable Peripheral Select
Bit 0 – MSTR Master/Slave Mode
Value Description
0
SPI is in Slave mode
1
SPI is in Master mode
SAM E70/S70/V70/V71 Family
Serial Peripheral Interface (SPI)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 993