Datasheet

are processed following a phase and a polarity defined respectively by the NCPHA and CPOL bits in SPI_CSR0.
Note that the fields BITS, CPOL and NCPHA of the other chip select registers (SPI_CSR1...SPI_CSR3)
have no
effect when the SPI is programmed in Slave mode.
The bits are shifted out on the MISO line and sampled on the MOSI line.
Note: For more information on SPI_CSRx.BITS, see the note in section SPI Chip Select Register.
When all bits are processed, the received data is transferred in SPI_RDR and the RDRF bit rises. If SPI_RDR has
not been read before new data is received, the Overrun Error Status (OVRES) bit in SPI_SR is set. As long as this
flag is set, data is loaded in SPI_RDR. The user must read SPI_SR to clear the OVRES bit.
When a transfer starts, the data shifted out is the data present in the internal shift register. If no data has been written
in SPI_TDR, the last data received is transferred. If no data has been received since the last reset, all bits are
transmitted low, as the internal shift register resets to 0.
When a first data is written in SPI_TDR, it is transferred immediately in the internal shift register and the TDRE flag
rises. If new data is written, it remains in SPI_TDR until a transfer occurs, i.e., NSS falls and there is a valid clock on
the SPCK pin. When the transfer occurs, the last data written in SPI_TDR is transferred in the internal shift register
and the TDRE flag rises. This enables frequent updates of critical variables with single transfers.
Then, new data is loaded in the internal shift register from SPI_TDR. If no character is ready to be transmitted, i.e.,
no character has been written in SPI_TDR since the last load from SPI_TDR to the internal shift register, SPI_TDR is
retransmitted. In this case the Underrun Error Status Flag (UNDES) is set in SPI_SR.
In Slave mode, if the NSS line rises and the received character length does not match the configuration defined in
SPI_CSR0.BITS the flag SFERR is set in SPI_SR.
The following figure shows a block diagram of the SPI when operating in Slave mode.
Figure 41-12. Slave Mode Functional Block Diagram
Shift Register
SPCK
SPIENS
LSB MSB
NSS
MOSI
SPI_RDR
RD
SPI
Clock
TDRE
SPI_TDR
TD
RDRF
OVRES
SPI_CSR0
CPOL
NCPHA
BITS
SPIEN
SPIDIS
MISO
41.7.5 Register Write Protection
To prevent any single software error from corrupting SPI behavior, certain registers in the address space can be
write-protected in the SPI W
rite Protection Mode Register (SPI_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the SPI Write Protection Status Register
(SPI_WPSR) is set and the WPVSRC field indicates the register in which the write access has been attempted.
The WPVS bit is automatically cleared after reading SPI_WPSR.
The following registers are write-protected when WPEN is set in SPI_WPMR:
• SPI Mode Register
• SPI Chip Select Register
The following register is write-protected when WPCREN is set in SPI_WPMR:
SAM E70/S70/V70/V71 Family
Serial Peripheral Interface (SPI)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 986