Datasheet

Figure 41-11. Peripheral Deselection
A
NPCS[0..n]
Write SPI_TDR
TDRE
NPCS[0..n]
Write SPI_TDR
TDRE
NPCS[0..n]
Write SPI_TDR
TDRE
DLYBCS
PCS = A
DLYBCS
DLYBCT
A
PCS = B
B
DLYBCS
PCS = A
DLYBCS
DLYBCT
A
PCS = B
B
DLYBCS
DLYBCT
PCS=A
A
DLYBCS
DLYBCT
A
PCS = A
AA
DLYBCT
A A
CSAAT = 0 and CSNAAT = 0
DLYBCT
A A
CSAAT = 1 and CSNAAT= 0 / 1
A
DLYBCS
PCS = A
DLYBCT
A A
CSAAT = 0 and CSNAAT = 1
NPCS[0..n]
Write SPI_TDR
TDRE
PCS = A
DLYBCT
A A
CSAAT = 0 and CSNAAT = 0
41.7.3.10 Mode Fault Detection
The SPI has the capability to operate in multimaster environment. Consequently, the NPCS0/NSS line must be
monitored. If one of the masters on the SPI bus is currently transmitting, the NPCS0/NSS line is low and the SPI
must not transmit any data. A mode fault is detected when the SPI is programmed in Master mode and a low level is
driven by an external master on the NPCS0/NSS signal. In multimaster environment, NPCS0, MOSI, MISO and
SPCK pins must be configured in open drain (through the PIO controller). When a mode fault is detected,
SPI_SR.MODF bit is set until SPI_SR is read and the SPI is automatically disabled until it is reenabled by setting
SPI_CR.SPIEN bit.
By default, the mode fault detection is enabled. The user can disable it by setting SPI_MR.MODFDIS bit.
41.7.4 SPI Slave Mode
When operating in Slave mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK).
The SPI waits until NSS goes active before receiving the serial clock from an external master
. When NSS falls, the
clock is validated and the data is loaded in SPI_RDR depending on the configuration of SPI_CSR0.BITS. These bits
SAM E70/S70/V70/V71 Family
Serial Peripheral Interface (SPI)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 985