Datasheet

The figure below shows the behavior of Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and
T
ransmission Register Empty (TXEMPTY) status flags within SPI_SR during an 8-bit data transfer in Fixed mode
without the DMA involved.
Figure 41-8. Status Register Flags Behavior
6
SPCK
MOSI
(
from master)
MISO
(from slave)
NPCS0
MSB
MSB
LSB
LSB
6
6
5
5
4
4
3
3
2
2
1
1
1 2 3 4 5 7 86
RDRF
TDRE
TXEMPTY
Write in
SPI_TDR
RDR read
shift register empty
41.7.3.3 Clock Generation
The SPI Baud rate clock is generated by dividing the peripheral clock by a value between 1 and 255.
If SPI_CSRx.SCBR is programmed to 1, the operating baud rate is peripheral clock (refer to the section “Electrical
Characteristics” for the SPCK maximum frequency). T
riggering a transfer while SPI_CSRx.SCBR is at 0 can lead to
unpredictable results.
At reset, SPI_CSRx.SCBR=0 and the user has to program it to a valid value before performing the first transfer.
The divisor can be defined independently for each chip select, as it has to be programmed in SPI_CSRx.SCBR. This
allows the SPI to automatically adapt the baud rate for each interfaced peripheral without reprogramming.
Related Links
58. Electrical Characteristics for SAM V70/V71
41.7.3.4 Transfer Delays
The following figure shows a chip select transfer change and consecutive transfers on the same chip select. Three
delays can be programmed to modify the transfer waveforms:
• Delay between the chip selects—programmable only once for all chip selects by writing field SPI_MR.DLYBCS.
The SPI slave device deactivation delay is managed through DLYBCS. If there is only one SPI slave device
connected to the master, DLYBCS does not need to be configured. If several slave devices are connected to a
master, DLYBCS must be configured depending on the highest deactivation delay. Refer to details on the SPI
slave device in the section “Electrical Characteristics”.
• Delay before SPCK—independently programmable for each chip select by writing SPI_CSRx.DLYBS. The SPI
slave device activation delay is managed through DLYBS. Refer to details on the SPI slave device in the section
“Electrical Characteristics” to define DLYBS.
• Delay between consecutive transfers—independently programmable for each chip select by writing
SPI_CSRx.DLYBCT. The time required by the SPI slave device to process received data is managed through
DLYBCT. This time depends on the SPI slave system activity.
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time.
SAM E70/S70/V70/V71 Family
Serial Peripheral Interface (SPI)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 981