Datasheet

41.7.3.1 Master Mode Block Diagram
Figure 41-6. Master Mode Block Diagram
Shift Register
SPCK
MOSI
LSB MSB
MISO
SPI_RDR
RD
SPI
Clock
TDRE
SPI_TDR
TD
RDRF
OVRES
SPI_CSRx
CPOL
NCPHA
BITS
Peripheral clock
Baud Rate Generator
SPI_CSRx
SCBR
NPCSx
NPCS0
NPCS0
0
1
PS
SPI_MR
PCS
SPI_TDR
PCS
MODF
Current
Peripheral
SPI_RDR
PCS
SPI_CSRx
CSAAT
PCSDEC
MODFDIS
MSTR
SAM E70/S70/V70/V71 Family
Serial Peripheral Interface (SPI)
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echnology Inc.
Datasheet
DS60001527D-page 979