Datasheet

19.4 Register Summary
Offset Name Bit Pos.
0x00 MATRIX_MCFG0
7:0 ULBT[2:0]
15:8
23:16
31:24
...
0x30 MATRIX_MCFG12
7:0 ULBT[2:0]
15:8
23:16
31:24
0x34
...
0x3F
Reserved
0x40 MATRIX_SCFG0
7:0 SLOT_CYCLE[6:0]
15:8 SLOT_CYCLE[8:7]
23:16 FIXED_DEFMSTR[3:0] DEFMSTR_TYPE[1:0]
31:24
0x44 MATRIX_SCFG1
7:0 SLOT_CYCLE[6:0]
15:8 SLOT_CYCLE[8:7]
23:16 FIXED_DEFMSTR[3:0] DEFMSTR_TYPE[1:0]
31:24
0x48 MATRIX_SCFG2
7:0 SLOT_CYCLE[6:0]
15:8 SLOT_CYCLE[8:7]
23:16 FIXED_DEFMSTR[3:0] DEFMSTR_TYPE[1:0]
31:24
0x4C MATRIX_SCFG3
7:0 SLOT_CYCLE[6:0]
15:8 SLOT_CYCLE[8:7]
23:16 FIXED_DEFMSTR[3:0] DEFMSTR_TYPE[1:0]
31:24
0x50 MATRIX_SCFG4
7:0 SLOT_CYCLE[6:0]
15:8 SLOT_CYCLE[8:7]
23:16 FIXED_DEFMSTR[3:0] DEFMSTR_TYPE[1:0]
31:24
0x54 MATRIX_SCFG5
7:0 SLOT_CYCLE[6:0]
15:8 SLOT_CYCLE[8:7]
23:16 FIXED_DEFMSTR[3:0] DEFMSTR_TYPE[1:0]
31:24
0x58 MATRIX_SCFG6
7:0 SLOT_CYCLE[6:0]
15:8 SLOT_CYCLE[8:7]
23:16 FIXED_DEFMSTR[3:0] DEFMSTR_TYPE[1:0]
31:24
0x5C MATRIX_SCFG7
7:0 SLOT_CYCLE[6:0]
15:8 SLOT_CYCLE[8:7]
23:16 FIXED_DEFMSTR[3:0] DEFMSTR_TYPE[1:0]
31:24
0x60 MATRIX_SCFG8
7:0 SLOT_CYCLE[6:0]
15:8 SLOT_CYCLE[8:7]
23:16 FIXED_DEFMSTR[3:0] DEFMSTR_TYPE[1:0]
31:24
0x64
...
0x7F
Reserved
0x80 MATRIX_PRAS0
7:0 M1PR[1:0] M0PR[1:0]
15:8 M3PR[1:0] M2PR[1:0]
23:16 M5PR[1:0] M4PR[1:0]
31:24 M7PR[1:0] M6PR[1:0]
SAM E70/S70/V70/V71 Family
Bus Matrix (MA
TRIX)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 97