Datasheet

40.14.15 HSMCI Interrupt Mask Register
Name: HSMCI_IMR
Offset: 0x4C
Reset: 0x0
Property: Read-only
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
Bit 31 30 29 28 27 26 25 24
UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY BLKOVRE
Access
Reset 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE
Access
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
CSRCV SDIOWAIT SDIOIRQA
Access
Reset 0 0 0
Bit 7 6 5 4 3 2 1 0
NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY
Access
Reset 0 0 0 0 0 0
Bit 31 – UNRE Underrun Interrupt Mask
Bit 30 – OVRE Overrun Interrupt Mask
Bit 29 – ACKRCVE
Boot Operation Acknowledge Error Interrupt Mask
Bit 28 – ACKRCV Boot Operation Acknowledge Received Interrupt Mask
Bit 27 – XFRDONE Transfer Done Interrupt Mask
Bit 26 – FIFOEMPTY FIFO Empty Interrupt Mask
Bit 24 – BLKOVRE DMA Block Overrun Error Interrupt Mask
Bit 23 – CSTOE Completion Signal Time-out Error Interrupt Mask
Bit 22 – DTOE Data Time-out Error Interrupt Mask
Bit 21 – DCRCE Data CRC Error Interrupt Mask
Bit 20 – RTOE Response Time-out Error Interrupt Mask
Bit 19 – RENDE Response End Bit Error Interrupt Mask
SAM E70/S70/V70/V71 Family
High-Speed Multimedia Card Interface (HSMCI)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 966