Datasheet

40.14.14 HSMCI Interrupt Disable Register
Name: HSMCI_IDR
Offset: 0x48
Property: Write-only
The following configuration values are valid for all listed bit names of this register:
0: No ef
fect.
1: Disables the corresponding interrupt.
Bit 31 30 29 28 27 26 25 24
UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY BLKOVRE
Access
Reset
Bit 23 22 21 20 19 18 17 16
CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE
Access
Reset
Bit 15 14 13 12 11 10 9 8
CSRCV SDIOWAIT SDIOIRQA
Access
Reset
Bit 7 6 5 4 3 2 1 0
NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY
Access
Reset
Bit 31 – UNRE Underrun Interrupt Disable
Bit 30 – OVRE Overrun Interrupt Disable
Bit 29 – ACKRCVE
Boot Acknowledge Error Interrupt Disable
Bit 28 – ACKRCV Boot Acknowledge Interrupt Disable
Bit 27 – XFRDONE Transfer Done Interrupt Disable
Bit 26 – FIFOEMPTY FIFO empty Interrupt Disable
Bit 24 – BLKOVRE DMA Block Overrun Error Interrupt Disable
Bit 23 – CSTOE Completion Signal Time out Error Interrupt Disable
Bit 22 – DTOE Data Time-out Error Interrupt Disable
Bit 21 – DCRCE Data CRC Error Interrupt Disable
Bit 20 – RTOE Response Time-out Error Interrupt Disable
Bit 19 – RENDE Response End Bit Error Interrupt Disable
Bit 18 – RCRCE Response CRC Error Interrupt Disable
SAM E70/S70/V70/V71 Family
High-Speed Multimedia Card Interface (HSMCI)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 964