Datasheet

Value Description
0
No completion signal received since last status read operation.
1
The device has issued a command completion signal on the command line.
Bit 12 – SDIOWAIT SDIO Read W
ait Operation Status
Value Description
0
Normal Bus operation.
1
The data bus has entered IO wait state.
Bit 8 – SDIOIRQA SDIO Interrupt for Slot A (cleared on read)
Value Description
0
No interrupt detected on SDIO Slot A.
1
An SDIO Interrupt on Slot A occurred.
Bit 5 – NOTBUSY HSMCI Not Busy
A block write operation uses a simple busy signalling of the write operation duration on the data (DA
T0) line: during a
data transfer block, if the card does not have a free data receive buffer, the card indicates this condition by pulling
down the data line (DAT0) to LOW. The card stops pulling down the data line as soon as at least one receive buffer
for the defined data transfer block length becomes free.
Refer to the MMC or SD Specification for more details concerning the busy behavior.
For all the read operations, the NOTBUSY flag is cleared at the end of the host command.
For the Infinite Read Multiple Blocks, the NOTBUSY flag is set at the end of the STOP_TRANSMISSION host
command (CMD12).
For the Single Block Reads, the NOTBUSY flag is set at the end of the data read block.
For the Multiple Block Reads with predefined block count, the NOTBUSY flag is set at the end of the last received
data block.
The NOTBUSY flag allows to deal with these different states.
Value Description
0
The HSMCI is not ready for new data transfer. Cleared at the end of the card response.
1
The HSMCI is ready for new data transfer. Set when the busy state on the data line has ended. This
corresponds to a free internal data receive buf
fer of the card.
Bit 4 – DTIP Data T
ransfer in Progress (cleared at the end of CRC16 calculation)
Value Description
0
No data transfer in progress.
1
The current data transfer is still in progress, including CRC16 calculation.
Bit 3 – BLKE Data Block Ended (cleared on read)
This flag must be used only for W
rite Operations.
Refer to the MMC or SD Specification for more details concerning the CRC Status.
Value Description
0
A data block transfer is not yet finished.
1
A data block transfer has ended, including the CRC16 Status transmission. The flag is set for each
transmitted CRC Status.
Bit 2 – TXRDY T
ransmit Ready (cleared by writing in HSMCI_TDR)
Value Description
0
The last data written in HSMCI_TDR has not yet been transferred in the Shift Register.
1
The last data written in HSMCI_TDR has been transferred in the Shift Register.
Bit 1 – RXRDY Receiver Ready (cleared by reading HSMCI_RDR)
Value Description
0
Data has not yet been received since the last read of HSMCI_RDR.
1
Data has been received since the last read of HSMCI_RDR.
Bit 0 – CMDRDY Command Ready (cleared by writing in HSMCI_CMDR)
SAM E70/S70/V70/V71 Family
High-Speed Multimedia Card Interface (HSMCI)
©
2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 960