Datasheet

If more than one master requests the slave bus, regardless of the respective masters priorities, no master will be
granted the slave bus for two consecutive runs. A master can only get back-to-back grants so long as it is the only
requesting master
.
19.3.3.2.1 Fixed Priority Arbitration
The fixed priority arbitration algorithm is the first and only arbitration algorithm applied between masters from distinct
priority pools. It is also used in priority pools other than the highest and lowest priority pools (intermediate priority
pools).
Fixed priority arbitration is used by the MATRIX arbiters to dispatch the requests from different masters to the same
slave by using the fixed priority defined by the user. If requests from two or more masters are active at the same time,
the master with the highest priority number is serviced first. If requests from two or more masters with the same
priority are active at the same time, the master with the highest number is serviced first.
For each slave, the priority of each master is defined in the MxPR field in the Priority Registers, MATRIX_PRAS and
MATRIX_PRBS.
19.3.3.2.2 Round-Robin Arbitration
Round-robin arbitration is only used in the highest and lowest priority pools. It allows the MATRIX arbiters to properly
dispatch requests from different masters to the same slave. If two or more master requests are active at the same
time in the priority pool, they are serviced in a round-robin increasing master number order.
19.3.4 System I/O Configuration
The System I/O Configuration register (CCFG_SYSIO) configures I/O lines in System I/O mode (such as JTAG,
ERASE, USB, etc.) or as general purpose I/O lines. Enabling or disabling the corresponding I/O lines in peripheral
mode or in PIO mode (PIO_PER or PIO_PDR registers) in the PIO controller as no effect. However, the direction
(input or output), pull-up, pull-down and other mode control is still managed by the PIO controller.
19.3.5 SMC NAND Flash Chip Select Configuration
The SMC Nand Flash Chip Select Configuration Register (CCFG_SMCNFCS) manages the chip select signal
(NCSx) and its assignment to NAND Flash.
Each NCSx may or may not be individually assigned to NAND Flash. When the NCSx is assigned to NAND Flash,
the signals NANDOE and NANDWE are used for the NCSx signals selected.
19.3.6 Configuration of Automatic Clock-off Mode
To reduce power consumption, MATRIX, Bridge and EFC automatic clock gating can be enabled by writing a ‘1’ to
bits MATCKG, BRIDCKG and EFCCKG, respectively, in the Dynamic Clock Gating register (CCFG_DYNCKG).
19.3.7 Register Write Protection
To prevent any single software error from corrupting MATRIX behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the Write Protection Mode Register (MATRIX_WPMR).
If a write access to a write-protected register is detected, the WPVS flag in the Write Protection Status Register
(MATRIX_WPSR) is set and the field WPVSRC indicates the register in which the write access has been attempted.
The WPVS flag is reset by writing the Bus Matrix Write Protect Mode Register (MATRIX_WPMR) with the appropriate
access key WPKEY.
The following registers can be write-protected:
• Bus Matrix Master Configuration Registers
• Bus Matrix Slave Configuration Registers
• Bus Matrix Priority Registers A For Slaves
• Bus Matrix Priority Registers B For Slaves
• Bus Matrix Master Remap Control Register
SAM E70/S70/V70/V71 Family
Bus Matrix (MA
TRIX)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 96