Datasheet

Value Description
1
Command Register is ready to operate and the data bus is in the idle state.
Bit 26 – FIFOEMPTY FIFO empty flag
Value Description
0
FIFO contains at least one byte.
1
FIFO is empty.
Bit 24 – BLKOVRE DMA Block Overrun Error (cleared on read)
Value Description
0
No error.
1
A new block of data is received and the DMA controller has not started to move the current pending
block, a block overrun is raised.
Bit 23 – CSTOE Completion Signal T
ime-out Error (cleared on read)
Value Description
0
No error.
1
The completion signal time-out set by CSTOCYC and CSTOMUL in HSMCI_CSTOR has been
exceeded.
Bit 22 – DTOE Data T
ime-out Error (cleared on read)
Value Description
0
No error.
1
The data time-out set by DTOCYC and DTOMUL in HSMCI_DTOR has been exceeded.
Bit 21 – DCRCE Data CRC Error (cleared on read)
Value Description
0
No error.
1
A CRC16 error has been detected in the last data block.
Bit 20 – RTOE Response T
ime-out Error (cleared by writing in HSMCI_CMDR)
Value Description
0
No error.
1
The response time-out set by MAXLAT in the HSMCI_CMDR has been exceeded.
Bit 19 – RENDE Response End Bit Error (cleared by writing in HSMCI_CMDR)
Value Description
0
No error.
1
The end bit of the response has not been detected.
Bit 18 – RCRCE Response CRC Error (cleared by writing in HSMCI_CMDR)
Value Description
0
No error.
1
A CRC7 error has been detected in the response.
Bit 17 – RDIRE Response Direction Error (cleared by writing in HSMCI_CMDR)
Value Description
0
No error.
1
The direction bit from card to host in the response has not been detected.
Bit 16 – RINDE Response Index Error (cleared by writing in HSMCI_CMDR)
Value Description
0
No error.
1
A mismatch is detected between the command index sent and the response index received.
Bit 13 – CSRCV CE-A
TA Completion Signal Received (cleared on read)
SAM E70/S70/V70/V71 Family
High-Speed Multimedia Card Interface (HSMCI)
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2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 959