Datasheet

40.14.12 HSMCI Status Register
Name: HSMCI_SR
Offset: 0x40
Reset: 0xC0E5
Property: Read-only
Bit 31 30 29 28 27 26 25 24
UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY BLKOVRE
Access
Reset 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE
Access
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
CSRCV SDIOWAIT SDIOIRQA
Access
Reset 0 0 0
Bit 7 6 5 4 3 2 1 0
NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY
Access
Reset 1 0 0 1 0 1
Bit 31 – UNRE Underrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL =
0)
If FERRCTRL = 1 in HSMCI_CFG, OVRE is cleared on read.
If FERRCTRL = 0 in HSMCI_CFG, OVRE is cleared by writing HSMCI_CMDR.
Value Description
0
No error.
1
At least one 8-bit data has been sent without valid information (not written).
Bit 30 – OVRE Overrun (if FERRCTRL = 1, cleared by writing in HSMCI_CMDR or cleared on read if FERRCTRL =
0)
If FERRCTRL = 1 in HSMCI_CFG, OVRE is cleared on read.
If FERRCTRL = 0 in HSMCI_CFG, OVRE is cleared by writing HSMCI_CMDR.
Value Description
0
No error.
1
At least one 8-bit received data has been lost (not read).
Bit 29 – ACKRCVE Boot Operation Acknowledge Error (cleared on read)
Value Description
0
No boot operation error since the last read of HSMCI_SR
1
Corrupted Boot Acknowledge signal received since the last read of HSMCI_SR.
Bit 28 – ACKRCV Boot Operation Acknowledge Received (cleared on read)
Value Description
0
No Boot acknowledge received since the last read of the HSMCI_SR.
1
A Boot acknowledge signal has been received since the last read of HSMCI_SR.
Bit 27 – XFRDONE T
ransfer Done flag
Value Description
0
A transfer is in progress.
SAM E70/S70/V70/V71 Family
High-Speed Multimedia Card Interface (HSMCI)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 958