Datasheet

40.14.9 HSMCI Response Register
Name: HSMCI_RSPR
Offset: 0x20
Reset: 0x0
Property: Read-only
Note: 1. The response register can be read by N accesses at the same HSMCI_RSPR or at consecutive addresses
(0x20 to 0x2C).
N depends on the size of the response.
Bit 31 30 29 28 27 26 25 24
RSP[31:24]
Access
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
RSP[23:16]
Access
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
RSP[15:8]
Access
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
RSP[7:0]
Access
Reset 0 0 0 0 0 0 0 0
Bits 31:0 – RSP[31:0] Response
SAM E70/S70/V70/V71 Family
High-Speed Multimedia Card Interface (HSMCI)
©
2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 955