Datasheet

40.14.8 HSMCI Completion Signal Timeout Register
Name: HSMCI_CSTOR
Offset: 0x1C
Reset: 0x0
Property: Read/Write
This register can only be written if the WPEN bit is cleared in the HSMCI W
rite Protection Mode Register.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
CSTOMUL[2:0] CSTOCYC[3:0]
Access
Reset 0 0 0 0 0 0 0
Bits 6:4 – CSTOMUL[2:0] Completion Signal T
imeout Multiplier
This field determines the maximum number of Master Clock cycles that the HSMCI waits between two data block
transfers. Its value is calculated by (CSTOCYC x Multiplier).
These fields determine the maximum number of Master Clock cycles that the HSMCI waits between the end of the
data transfer and the assertion of the completion signal. The data transfer comprises data phase and the optional
busy phase. If a non-DATA ATA command is issued, the HSMCI starts waiting immediately after the end of the
response until the completion signal.
Multiplier is defined by CSTOMUL as shown in the following table:
If the data time-out set by CSTOCYC and CSTOMUL has been exceeded, the Completion Signal Time-out Error flag
(CSTOE) in the HSMCI Status Register (HSMCI_SR) rises.
Value Name Description
0
1 CSTOCYC x 1
1
16 CSTOCYC x 16
2
128 CSTOCYC x 128
3
256 CSTOCYC x 256
4
1024 CSTOCYC x 1024
5
4096 CSTOCYC x 4096
6
65536 CSTOCYC x 65536
7
1048576 CSTOCYC x 1048576
Bits 3:0 – CSTOCYC[3:0] Completion Signal T
imeout Cycle Number
This field determines the maximum number of Master Clock cycles that the HSMCI waits between two data block
transfers. Its value is calculated by (CSTOCYC x Multiplier).
SAM E70/S70/V70/V71 Family
High-Speed Multimedia Card Interface (HSMCI)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 954