Datasheet

Bit 18 – TRDIR T
ransfer Direction
0 (WRITE): Write.
1 (READ): Read.
Bits 17:16 – TRCMD[1:0] Transfer Command
Value Name Description
0
NO_DATA No data transfer
1
START_DATA Start data transfer
2
STOP_DATA Stop data transfer
3
Reserved Reserved
Bit 12 – MAXLAT Max Latency for Command to Response
0 (5): 5-cycle max latency
.
1 (64): 64-cycle max latency.
Bit 11 – OPDCMD Open Drain Command
0 (PUSHPULL): Push pull command.
1 (OPENDRAIN): Open drain command.
Bits 10:8 – SPCMD[2:0] Special Command
Value Name Description
0
STD Not a special CMD.
1
INIT Initialization CMD:
74 clock cycles for initialization sequence.
2
SYNC Synchronized CMD:
W
ait for the end of the current data block transfer before sending the pending command.
3
CE_ATA CE-ATA Completion Signal disable Command.
The host cancels the ability for the device to return a command completion signal on the
command line.
4
IT_CMD Interrupt command:
Corresponds to the Interrupt Mode (CMD40).
5
IT_RESP Interrupt response:
Corresponds to the Interrupt Mode (CMD40).
6
BOR Boot Operation Request.
Start a boot operation mode, the host processor can read boot data from the MMC device
directly.
7
EBO End Boot Operation.
This command allows the host processor to terminate the boot operation mode.
Bits 7:6 – RSPTYP[1:0] Response T
ype
Value Name Description
0
NORESP No response
1
48_BIT 48-bit response
2
136_BIT 136-bit response
3
R1B R1b response type
Bits 5:0 – CMDNB[5:0] Command Number
This is the command index.
SAM E70/S70/V70/V71 Family
High-Speed Multimedia Card Interface (HSMCI)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 952