Datasheet

40.14.6 HSMCI Command Register
Name: HSMCI_CMDR
Offset: 0x14
Property: Write-only
This register is write-protected while CMDRDY is 0 in HSMCI_SR. If an Interrupt command is sent, this register is
only writable by an interrupt response (field SPCMD). This means that the current command execution cannot be
interrupted or modified.
Bit 31 30 29 28 27 26 25 24
BOOT_ACK ATACS IOSPCMD[1:0]
Access
Reset
Bit 23 22 21 20 19 18 17 16
TRTYP[2:0] TRDIR TRCMD[1:0]
Access
Reset
Bit 15 14 13 12 11 10 9 8
MAXLAT OPDCMD SPCMD[2:0]
Access
Reset
Bit 7 6 5 4 3 2 1 0
RSPTYP[1:0] CMDNB[5:0]
Access
Reset
Bit 27 – BOOT_ACK Boot Operation Acknowledge
The master can choose to receive the boot acknowledge from the slave when a Boot Request command is issued.
When set to one this field indicates that a Boot acknowledge is expected within a programmable amount of time
defined with DT
OMUL and DTOCYC fields located in the HSMCI_DTOR. If the acknowledge pattern is not received
then an acknowledge timeout error is raised. If the acknowledge pattern is corrupted then an acknowledge pattern
error is set.
Bit 26 – ATACS ATA with Command Completion Signal
0 (NORMAL): Normal operation mode.
1 (COMPLETION): This bit indicates that a completion signal is expected within a programmed amount of time
(HSMCI_CSTOR).
Bits 25:24 – IOSPCMD[1:0] SDIO Special Command
Value Name Description
0
STD Not an SDIO Special Command
1
SUSPEND SDIO Suspend Command
2
RESUME SDIO Resume Command
Bits 21:19 – TRTYP[2:0] T
ransfer Type
Value Name Description
0
SINGLE MMC/SD Card Single Block
1
MULTIPLE MMC/SD Card Multiple Block
2
STREAM MMC Stream
4
BYTE SDIO Byte
5
BLOCK SDIO Block
SAM E70/S70/V70/V71 Family
High-Speed Multimedia Card Interface (HSMCI)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 951