Datasheet

Figure 40-12. XFRDONE During a Write Access
CMD line
Card response
CMDRDY flag
Data bus - D0
1st Block
NOTBUSY flag
XFRDONE flag
The CMDRDY flag is released 8 tbit after the end of the card response.
Last Block
D0
1st Block
Last Block
D0 is tied by the card
D0 is released
HSMCI write CMD
40.13 Register Write Protection
To prevent any single software error from corrupting HSMCI behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the HSMCI Write Protection Mode Register (HSMCI_WPMR).
If a write access to a write-protected register is detected, the WPVS bit in the HSMCI Write Protection Status
Register (HSMCI_WPSR) is set and the field WPVSRC indicates the register in which the write access has been
attempted.
The WPVS bit is automatically cleared after reading the HSMCI_WPSR.
The following registers can be protected:
• HSMCI Mode Register
• HSMCI Data Timeout Register
• HSMCI SDCard/SDIO Register
• HSMCI Completion Signal Timeout Register
• HSMCI DMA Configuration Register
• HSMCI Configuration Register
SAM E70/S70/V70/V71 Family
High-Speed Multimedia Card Interface (HSMCI)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 942