Datasheet

40.10.1 Executing an ATA Polling Command
1. Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for 8 KB of DATA.
2.
Read the ATA status register until DRQ is set.
3. Issue RW_MULTIPLE_BLOCK (CMD61) to transfer DATA.
4. Read the ATA status register until DRQ && BSY are configured to 0.
40.10.2 Executing an ATA Interrupt Command
1. Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for 8 KB of DATA with nIEN field set to
zero to enable the command completion signal in the device.
2.
Issue RW_MULTIPLE_BLOCK (CMD61) to transfer DATA.
3. Wait for Completion Signal Received Interrupt.
40.10.3 Aborting an ATA Command
If the host needs to abort an ATA command prior to the completion signal it must send a special command to avoid
potential collision on the command line. The SPCMD field of the HSMCI_CMDR must be set to 3 to issue the CE-A
TA
completion Signal Disable Command.
40.10.4 CE-ATA Error Recovery
Several methods of ATA command failure may occur, including:
•
No response to an MMC command, such as RW_MULTIPLE_REGISTER (CMD60).
• CRC is invalid for an MMC command or response.
• CRC16 is invalid for an MMC data packet.
• ATA Status register reflects an error by setting the ERR bit to one.
• The command completion signal does not arrive within a host specified time out period.
Error conditions are expected to happen infrequently. Thus, a robust error recovery mechanism may be used for each
error event. The recommended error recovery procedure after a timeout is:
• Issue the command completion signal disable if nIEN was cleared to zero and the RW_MULTIPLE_BLOCK
(CMD61) response has been received.
• Issue STOP_TRANSMISSION (CMD12) and successfully receive the R1 response.
• Issue a software reset to the CE-ATA device using FAST_IO (CMD39).
If STOP_TRANMISSION (CMD12) is successful, then the device is again ready for ATA commands. However, if the
error recovery procedure does not work as expected or there is another timeout, the next step is to issue
GO_IDLE_STATE (CMD0) to the device. GO_IDLE_STATE (CMD0) is a hard reset to the device and completely
resets all device states.
Note that after issuing GO_IDLE_STATE (CMD0), all device initialization needs to be completed again. If the CE-ATA
device completes all MMC commands correctly but fails the ATA command with the ERR bit set in the ATA Status
register, no error recovery action is required. The ATA command itself failed implying that the device could not
complete the action requested, however, there was no communication or protocol failure. After the device signals an
error by setting the ERR bit to one in the ATA Status register, the host may attempt to retry the command.
40.11 HSMCI Boot Operation Mode
In boot operation mode, the processor can read boot data from the slave (MMC device) by keeping the CMD line low
after power-on before issuing CMD1. The data can be read from either the boot area or user area, depending on
register setting.
40.11.1 Boot Procedure, Processor Mode
1. Configure the HSMCI data bus width programming SDCBUS Field in the HSMCI_SDCR. The
BOOT_BUS_WIDTH field located in the device Extended CSD register must be set accordingly
.
2. Set the byte count to 512 bytes and the block count to the desired number of blocks, writing BLKLEN and
BCNT fields of the HSMCI_BLKR.
SAM E70/S70/V70/V71 Family
High-Speed Multimedia Card Interface (HSMCI)
©
2019 Microchip Technology Inc.
Datasheet
DS60001527D-page 940