Datasheet

40. High-Speed Multimedia Card Interface (HSMCI)
40.1 Description
The High Speed Multimedia Card Interface (HSMCI) supports the MultiMedia Card (MMC) Specification V4.3, the SD
Memory Card Specification V2.0, the SDIO V2.0 specification and CE-A
TA V1.1.
The HSMCI includes a command register, response registers, data registers, timeout counters and error detection
logic that automatically handle the transmission of commands and, when required, the reception of the associated
responses and data with a limited processor overhead.
The HSMCI operates at a rate of up to Master Clock divided by 2 and supports the interfacing of 1 slot(s). Each slot
may be used to interface with a High Speed MultiMedia Card bus (up to 30 Cards) or with an SD Memory Card. A bit
field in the SD Card Register performs this selection.
The SD Memory Card communication is based on a 9-pin interface (clock, command, four data and three power
lines) and the High Speed MultiMedia Card on a 7-pin interface (clock, command, one data, three power lines and
one reserved for future use).
The SD Memory Card interface also supports High Speed MultiMedia Card operations. The main differences
between SD and High Speed MultiMedia Cards are the initialization process and the bus topology.
HSMCI fully supports CE-ATA Revision 1.1, built on the MMC System Specification v4.0. The module includes
dedicated hardware to issue the command completion signal and capture the host command completion signal
disable.
40.2 Embedded Characteristics
• Compatible with MultiMedia Card Specification Version 4.3
• Compatible with SD Memory Card Specification Version 2.0
• Compatible with SDIO Specification Version 2.0
• Compatible with CE-ATA Specification 1.1
• Cards Clock Rate Up to Master Clock Divided by 2
• Boot Operation Mode Support
• High Speed Mode Support
• Embedded Power Management to Slow Down Clock Rate When Not Used
• Supports 1 Multiplexed Slot(s)
– Each Slot for either a High Speed MultiMedia Card Bus (Up to 30 Cards) or an SD Memory Card
• Support for Stream, Block and Multi-block Data Read and Write
• – Minimizes Processor Intervention for Large Buffer Transfers
• Built in FIFO (from 16 to 256 bytes) with Large Memory Aperture Supporting Incremental Access
• Support for CE-ATA Completion Signal Disable Command
• Protection Against Unexpected Modification On-the-Fly of the Configuration Registers
SAM E70/S70/V70/V71 Family
High-Speed Multimedia Card Interface (HSMCI)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 926