Datasheet

Bit 1 – CHANN_ACT Channel Active Status

When a packet transfer is ended, this bit is automatically reset.

When a packet transfer cannot be completed due to an END_BF_ST

, this flag stays set during the next channel

descriptor load (if any) and potentially until completion of a USBHS packet transfer, if allowed by the new descriptor.

Value Description

The DMA channel is no longer trying to source the packet data.

The DMA channel is currently trying to source packet data, i.e., selected as the highest-priority

requesting channel.

Bit 0 – CHANN_ENB Channel Enable Status

When any transfer is ended either due to an elapsed byte count or to completion of a USBHS device-initiated

transfer

, this bit is automatically reset.

This bit is normally set or cleared by writing into the USBHS_HSTDMACONTROLx.CHANN_ENB bit field either by

software or descriptor loading.

If a channel request is currently serviced when the USBHS_HSTDMACONTROLx.CHANN_ENB bit is cleared, the

DMA FIFO buffer is drained until it is empty, then this status bit is cleared.

Value Description

If cleared, the DMA channel no longer transfers data, and may load the next descriptor if the

USBHS_HSTDMACONTROLx.LDNXT_DSC bit is set.

If set, the DMA channel is currently enabled and transfers data upon request.

SAM E70/S70/V70/V71 Family

USB High-Speed Interface (USBHS)

echnology Inc.

Datasheet

DS60001527D-page 925