Datasheet

Value Description
0
Completion of a USBHS device-initiated buffer transfer does not trigger any interrupt at
USBHS_HSTDMAST
ATUSx.END_TR_ST rising.
1
An interrupt is sent after the buffer transfer is complete, if the USBHS device has ended the buffer
transfer.
Bit 3 – END_B_EN End of Buf
fer Enable Control
This is mainly for short packet OUT validations initiated by the DMA reaching the end of buffer, but could be used for
IN packet truncation (discarding of unwanted packet data) at the end of DMA buffer.
Value Description
0
DMA Buffer End has no impact on USB packet transfer.
1
The pipe can validate the packet (according to the values programmed in the
USBHS_HSTPIPCFGx.AUT
OSW and USBHS_HSTPIPIMRx.SHORTPACKETIE fields) at DMA Buffer
End, i.e., when USBHS_HSTDMASTATUS.BUFF_COUNT reaches 0.
Bit 2 – END_TR_EN End of T
ransfer Enable Control (OUT transfers only)
When set, a BULK or INTERRUPT short packet closes the current buffer and the
USBHS_HSTDMASTATUSx.END_TR_ST flag is raised.
This is intended for a USBHS non-prenegotiated USB transfer size.
Value Description
0
USB end of transfer is ignored.
1
The USBHS device can put an end to the current buffer transfer.
Bit 1 – LDNXT_DSC Load Next Channel T
ransfer Descriptor Enable Command
If the CHANN_ENB bit is cleared, the next descriptor is loaded immediately upon transfer request.
DMA Channel Control Command Summary:
Value LDNXT_DSC Value CHANN_ENB Name Description
0 0 STOP_NOW Stop now
0 1 RUN_AND_STOP Run and stop at end of buffer
1 0 LOAD_NEXT_DESC Load next descriptor now
1 1 RUN_AND_LINK Run and link at end of buffer
Value Description
0
No channel register is loaded after the end of the channel transfer.
1
The channel controller loads the next descriptor after the end of the current transfer, i.e., when the
USBHS_HSTDMAST
ATUS.CHANN_ENB bit is reset.
Bit 0 – CHANN_ENB Channel Enable Command
If the LDNXT_DSC bit has been cleared by descriptor loading, the firmware has to set the corresponding
CHANN_ENB bit to start the described transfer
, if needed.
If the LDNXT_DSC bit is cleared, the channel is frozen and the channel registers may then be read and/or written
reliably as soon as both the USBHS_HSTDMASTATUS.CHANN_ENB and the CHANN_ACT flags read as 0.
If a channel request is currently serviced when this bit is cleared, the DMA FIFO buffer is drained until it is empty,
then the USBHS_HSTDMASTATUS.CHANN_ENB bit is cleared.
If the LDNXT_DSC bit is set or after it has been cleared, the currently loaded descriptor is skipped (no data transfer
occurs) and the next descriptor is immediately loaded.
Value Description
0
The DMA channel is disabled and no transfer occurs upon request. This bit is also cleared by hardware
when the channel source bus is disabled at the end of the buf
fer.
1
The USBHS_HSTDMASTATUS.CHANN_ENB bit is set, enabling DMA channel data transfer. Then,
any pending request starts the transfer. This may be used to start or resume any requested transfer.
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 923