Datasheet
39.6.67 Host DMA Channel x Control Register
Name: USBHS_HSTDMACONTROLx
Offset: 0x0708 + x*0x10 [x=0..6]
Reset: 0
Property: Read/Write
Bit 31 30 29 28 27 26 25 24
BUFF_LENGTH[15:8]
Access
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
BUFF_LENGTH[7:0]
Access
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN END_TR_EN LDNXT_DSC CHANN_ENB
Access
Reset 0 0 0 0 0 0 0 0
Bits 31:16 – BUFF_LENGTH[15:0] Buf
fer Byte Length (Write-only)
This field determines the number of bytes to be transferred until end of buffer. The maximum channel transfer size
(32 KBytes) is reached when this field is 0 (default value). If the transfer size is unknown, this field should be set to 0,
but the transfer end may occur earlier under USB device control.
When this field is written, the USBHS_HSTDMASTATUSx.BUFF_COUNT field is updated with the write value.
Notes: 1. Bits [31:2] are only writable when issuing a channel Control Command other than “Stop Now”.
2. For reliability, it is highly recommended to wait for both the USBHS_HSTDMASTATUSx.CHAN_ACT and the
CHAN_ENB flags to be at 0, thus ensuring the channel has been stopped before issuing a command other than
“Stop Now”.
Bit 7 – BURST_LCK Burst Lock Enable
Value Description
0
The DMA never locks the bus access.
1
USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and
maximization of fly-by AHB burst duration.
Bit 6 – DESC_LD_IT Descriptor Loaded Interrupt Enable
Value Description
0
USBHS_HSTDMASTATUSx.DESC_LDST rising does not trigger any interrupt.
1
An interrupt is generated when a descriptor has been loaded from the bus.
Bit 5 – END_BUFFIT End of Buf
fer Interrupt Enable
Value Description
0
USBHS_HSTDMASTATUSx.END_BF_ST rising does not trigger any interrupt.
1
An interrupt is generated when USBHS_HSTDMASTATUSx.BUFF_COUNT reaches zero.
Bit 4 – END_TR_IT End of T
ransfer Interrupt Enable
Use when the receive size is unknown.
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 922