Datasheet

39.6.66 Host DMA Channel x Address Register
Name: USBHS_HSTDMAADDRESSx
Offset: 0x0704 + x*0x10 [x=0..6]
Reset: 0
Property: Read/Write
Bit 31 30 29 28 27 26 25 24
BUFF_ADD[31:24]
Access
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
BUFF_ADD[23:16]
Access
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
BUFF_ADD[15:8]
Access
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
BUFF_ADD[7:0]
Access
Reset 0 0 0 0 0 0 0 0
Bits 31:0 – BUFF_ADD[31:0] Buf
fer Address
This field determines the AHB bus starting address of a DMA channel transfer.
Channel start and end addresses may be aligned on any byte boundary.
The firmware can write this field only when the USBHS_HSTDMASTATUS.CHANN_ENB bit is cleared.
This field is updated at the end of the address phase of the current access to the AHB bus. It is incremented by the
access byte width. The access width is 4 bytes (or less) at packet start or end, if the start or end address is not
aligned on a word boundary.
The packet start address is either the channel start address or the next channel address to be accessed in the
channel buffer.
The packet end address is either the channel end address or the latest channel address accessed in the channel
buffer.
The channel start address is written by software or loaded from the descriptor. The channel end address is either
determined by the end of buffer or the USB device, or by the USB end of transfer if the
USBHS_HSTDMACONTROLx.END_TR_EN bit is set.
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 921