Datasheet

...........continued
Master Index Name
6 ISI DMA
7 Media LB
8 USB DMA
9 Ethernet MAC DMA
10 CAN0 DMA
11 CAN1 DMA
12 Cortex-M7
Note: Master 12 (Cortex-M7) is only on revision B.
19.2.2 Matrix Slaves
The MATRIX manages the slaves listed in the following table. Each slave has its own arbiter, providing a different
arbitration per slave.
T
able 19-2. Bus Matrix Slaves
Slave Index Name
0 Internal SRAM
1 Internal SRAM
2 Internal ROM
3 Internal Flash
4 USB High Speed Dual Port RAM (DPR)
5 External Bus Interface
6 QSPI
7 Peripheral Bridge
8 AHB Slave
19.2.3 Master to Slave Access
The following table provides valid paths for master to slave accesses. The paths shown as “-” are forbidden or not
wired.
T
able 19-3. Master to Slave Access
Masters 0 1 2 3 4 5 6 7 8 9 10 11 12
Slaves Cortex-
M7
Cortex-
M7
Cortex-M7
Peripheral
Port
ICM Central
DMA IF0
Central
DMA IF1
ISI
DMA
MediaLB
DMA
USB
DMA
GMAC
DMA
CAN0
DMA
CAN1
DMA
Cortex-
M7
0 Internal
SRAM
– – – X X – – – – – – – –
1 Internal
SRAM
– – – – – X X X X X X X –
2 Internal ROM X – – – – – – – – – – – –
3 Internal Flash X – – X – X – – X X – – –
SAM E70/S70/V70/V71 Family
Bus Matrix (MA
TRIX)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 92