Datasheet

39.6.60 Host Pipe x Enable Register (Control, Bulk Pipes)
Name: USBHS_HSTPIPIERx
Offset: 0x05F0 + x*0x04 [x=0..9]
Reset: 0
Property: Read/Write
This register view is relevant only if PTYPE = 0x0 or 0x2 in ”Host Pipe x Configuration Register”.
For additional information, see ”Host Pipe x Mask Register (Control, Bulk Pipes)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No ef
fect.
1: Sets the corresponding bit in USBHS_HSTPIPIMRx.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
RSTDTS PFREEZES PDISHDMAS
Access
Reset 0 0 0
Bit 15 14 13 12 11 10 9 8
NBUSYBKES
Access
Reset 0
Bit 7 6 5 4 3 2 1 0
SHORTPACKE
TIES
RXSTALLDES OVERFIES NAKEDES PERRES TXSTPES TXOUTES RXINES
Access
Reset 0 0 0 0 0 0 0 0
Bit 18 – RSTDTS Reset Data T
oggle Enable
Bit 17 – PFREEZES Pipe Freeze Enable
Bit 16 – PDISHDMAS Pipe Interrupts Disable HDMA Request Enable
Bit 12 – NBUSYBKES Number of Busy Banks Enable
Bit 7 – SHORTPACKETIES Short Packet Interrupt Enable
Bit 6 – RXSTALLDES Received STALLed Interrupt Enable
Bit 5 – OVERFIES Overflow Interrupt Enable
Bit 4 – NAKEDES NAKed Interrupt Enable
Bit 3 – PERRES Pipe Error Interrupt Enable
Bit 2 – TXSTPES Transmitted SETUP Interrupt Enable
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 911