Datasheet

19. Bus Matrix (MATRIX)
19.1 Description
The Bus Matrix (MATRIX) implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel
access paths between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The
MA
TRIX interconnects 13 AHB masters to 9 AHB slaves. The normal latency to connect a master to a slave is one
cycle. The exception is the default master of the accessed slave which is connected directly (zero cycle latency).
The MATRIX user interface is compliant with ARM Advanced Peripheral Bus.
19.2 Embedded Characteristics
• 13 Masters
•
9 Slaves
• One Decoder for Each Master
• Several Possible Boot Memories for Each Master before Remap
• One Remap Function for Each Master
• Support for Long Bursts of 32, 64, 128 and up to the 256-beat Word Burst AHB Limit
• Enhanced Programmable Mixed Arbitration for Each Slave
– Round-Robin
– Fixed Priority
• Programmable Default Master for Each Slave
– No Default Master
– Last Accessed Default Master
– Fixed Default Master
• Deterministic Maximum Access Latency for Masters
• Zero or One Cycle Arbitration Latency for the First Access of a Burst
• Bus Lock Forwarding to Slaves
• Master Number Forwarding to Slaves
• Configurable Automatic Clock-off Mode for Power Reduction
• One Special Function Register for Each Slave (not dedicated)
• Register Write Protection
19.2.1 Matrix Masters
The MATRIX manages the masters listed in he following table. Each master can perform an access to an available
slave concurrently with other masters. lists the available masters.
Each master has its own specifically-defined decoder. To simplify addressing, all the masters have the same
decodings.
Table 19-1. Bus Matrix Masters
Master Index Name
0 Cortex-M7
1 Cortex-M7
2 Cortex-M7 Peripheral Port
3 Integrated Check Monitor
4, 5 XDMAC
SAM E70/S70/V70/V71 Family
Bus Matrix (MA
TRIX)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 91