Datasheet

39.6.58 Host Pipe x Disable Register (Interrupt Pipes)
Name: USBHS_HSTPIPIDRx (INTPIPES)
Offset: 0x0620 + x*0x04 [x=0..9]
Reset: 0
Property: Read/Write
This register view is relevant only if PTYPE = 0x3 in ”Host Pipe x Configuration Register”.
For additional information, see ”Host Pipe x Mask Register (Interrupt Pipes)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No ef
fect.
1: Clears the corresponding bit in USBHS_HSTPIPIMRx.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
PFREEZEC PDISHDMAC
Access
Reset 0 0
Bit 15 14 13 12 11 10 9 8
FIFOCONC NBUSYBKEC
Access
Reset 0 0
Bit 7 6 5 4 3 2 1 0
SHORTPACKE
TIEC
RXSTALLDEC OVERFIEC NAKEDEC PERREC UNDERFIEC TXOUTEC RXINEC
Access
Reset 0 0 0 0 0 0 0 0
Bit 17 – PFREEZEC Pipe Freeze Disable
Bit 16 – PDISHDMAC
Pipe Interrupts Disable HDMA Request Disable
Bit 14 – FIFOCONC FIFO Control Disable
Bit 12 – NBUSYBKEC Number of Busy Banks Disable
Bit 7 – SHORTPACKETIEC Short Packet Interrupt Disable
Bit 6 – RXSTALLDEC Received STALLed Interrupt Disable
Bit 5 – OVERFIEC Overflow Interrupt Disable
Bit 4 – NAKEDEC NAKed Interrupt Disable
Bit 3 – PERREC Pipe Error Interrupt Disable
Bit 2 – UNDERFIEC Underflow Interrupt Disable
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 907