Datasheet

0: Cleared when USBHS_HSTPIPIDR.FIFOCONC = 1. This sends the FIFO data and switches the bank.
1: Set when the current bank is free, at the same time as USBHS_HSTPIPISR.TXOUTI or TXSTPI.
For IN pipes:
0: Cleared when USBHS_HSTPIPIDR.FIFOCONC = 1. This frees the current bank and switches to the next bank.
1: Set when a new IN message is stored in the current bank, at the same time as USBHS_HSTPIPISR.RXINI.
Bit 12 – NBUSYBKE
Number of Busy Banks Interrupt Enable
Value Description
0
Cleared when USBHS_HSTPIPIDR.NBUSYBKEC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.NBUSYBKE).
1
Set when USBHS_HSTPIPIER.NBUSYBKES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.NBUSYBKE).
Bit 7 – SHORTPACKETIE Short Packet Interrupt Enable
If this bit is set for non-control OUT pipes, a short packet transmission is guaranteed upon ending a DMA transfer
,
thus signaling an end of transfer, provided that the End of DMA Buffer Output Enable
(USBHS_HSTDMACONTROL.END_B_EN) bit and the Automatic Switch (USBHS_HSTPIPCFG.AUTOSW) bit = 1.
Value Description
0
Cleared when USBHS_HSTPIPIDR.SHORTPACKETEC = 1. This disables the Transmitted interrupt
Data IT (USBHS_HSTPIPIMR.SHOR
TPACKETE).
1
Set when USBHS_HSTPIPIER.SHORTPACKETIES = 1. This enables the Transmitted IN Data
interrupt (USBHS_HSTPIPIMR.SHORTPACKETIE).
Bit 6 – CRCERRE CRC Error Interrupt Enable
Value Description
0
Cleared when USBHS_HSTPIPIDR.CRCERREC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.CRCERRE).
1
Set when USBHS_HSTPIPIER.CRCERRES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.CRCERRE).
Bit 5 – OVERFIE Overflow Interrupt Enable
Value Description
0
Cleared when USBHS_HSTPIPIDR.OVERFIEC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.OVERFIE).
1
Set when USBHS_HSTPIPIER.OVERFIES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.OVERFIE).
Bit 4 – NAKEDE NAKed Interrupt Enable
Value Description
0
Cleared when USBHS_HSTPIPIDR.NAKEDEC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.NAKEDE).
1
Set when USBHS_HSTPIPIER.NAKEDES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.NAKEDE).
Bit 3 – PERRE Pipe Error Interrupt Enable
Value Description
0
Cleared when USBHS_HSTPIPIDR.PERREC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.PERRE).
1
Set when USBHS_HSTPIPIER.PERRES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.PERRE).
Bit 2 – UNDERFIE Underflow Interrupt Enable
Value Description
0
Cleared when USBHS_HSTPIPIDR.UNDERFIEC = 1. This disables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.UNDERFIE).
1
Set when USBHS_HSTPIPIER.UNDERFIES = 1. This enables the Transmitted IN Data interrupt
(USBHS_HSTPIPIMR.UNDERFIE).
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 903