Datasheet

39.6.55 Host Pipe x Mask Register (Interrupt Pipes)
Name: USBHS_HSTPIPIMRx (INTPIPES)
Offset: 0x05C0 + x*0x04 [x=0..9]
Reset: 0
Property: Read/Write
This register view is relevant only if PTYPE = 0x3 in ”Host Pipe x Configuration Register”.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
RSTDT PFREEZE PDISHDMA
Access
Reset 0 0 0
Bit 15 14 13 12 11 10 9 8
FIFOCON NBUSYBKE
Access
Reset 0 0
Bit 7 6 5 4 3 2 1 0
SHORTPACKE
TIE
RXSTALLDE OVERFIE NAKEDE PERRE UNDERFIE TXOUTE RXINE
Access
Reset 0 0 0 0 0 0 0 0
Bit 18 – RSTDT Reset Data T
oggle
Value Description
0
0: No reset of the Data Toggle is ongoing.
1
Set when USBHS_HSTPIPIER.RSTDTS = 1. This resets the Data Toggle to its initial value for the
current pipe.
Bit 17 – PFREEZE Pipe Freeze
This freezes the pipe request generation.
Value Description
0
Cleared when USBHS_HSTPIPIDR.PFREEZEC = 1. This enables the pipe request generation.
1
Set when one of the following conditions is met:
• USBHS_HSTPIPIER.PFREEZES = 1
• The pipe is not configured.
• A ST
ALL handshake has been received on the pipe.
• An error has occurred on the pipe (USBHS_HSTPIPISR.PERRI = 1).
• (INRQ+1) in requests have been processed.
• A Pipe Reset (USBHS_HSTPIP.PRSTx rising) has occurred.
• A Pipe Enable (USBHS_HSTPIP.PEN rising) has occurred.
Bit 16 – PDISHDMA Pipe Interrupts Disable HDMA Request Enable
See the USBHS_DEVEPTIMR.EPDISHDMA bit description.
Bit 14 – FIFOCON
FIFO Control
For OUT and SETUP pipes:
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 899