Datasheet

39.6.51 Host Pipe x Set Register (Control, Bulk Pipes)
Name: USBHS_HSTPIPIFRx
Offset: 0x0590
Reset: 0
Property: Read/Write
This register view is relevant only if PTYPE = 0x0 or 0x2 in ”Host Pipe x Configuration Register”.
For additional information, see ”Host Pipe x Status Register (Control, Bulk Pipes)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No ef
fect.
1: Sets the corresponding bit in USBHS_HSTPIPISRx, which may be useful for test or debug purposes.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
NBUSYBKS
Access
Reset 0
Bit 7 6 5 4 3 2 1 0
SHORTPACKE
TIS
RXSTALLDIS OVERFIS NAKEDIS PERRIS TXSTPIS TXOUTIS RXINIS
Access
Reset 0 0 0 0 0 0 0 0
Bit 12 – NBUSYBKS Number of Busy Banks Set
Bit 7 – SHORTP
ACKETIS Short Packet Interrupt Set
Bit 6 – RXSTALLDIS Received STALLed Interrupt Set
Bit 5 – OVERFIS Overflow Interrupt Set
Bit 4 – NAKEDIS NAKed Interrupt Set
Bit 3 – PERRIS Pipe Error Interrupt Set
Bit 2 – TXSTPIS Transmitted SETUP Interrupt Set
Bit 1 – TXOUTIS Transmitted OUT Data Interrupt Set
Bit 0 – RXINIS Received IN Data Interrupt Set
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 893