Datasheet

39.6.48 Host Pipe x Clear Register (Control, Bulk Pipes)
Name: USBHS_HSTPIPICRx
Offset: 0x0560 + x*0x04 [x=0..9]
Reset: 0
Property: Read/Write
This register view is relevant only if PTYPE = 0x0 or 0x2 in ”Host Pipe x Configuration Register”.
For additional information, see ”Host Pipe x Status Register (Control, Bulk Pipes)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No ef
fect.
1: Clears the corresponding bit in USBHS_HSTPIPISRx.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
SHORTPACKE
TIC
RXSTALLDIC OVERFIC NAKEDIC TXSTPIC TXOUTIC RXINIC
Access
Reset 0 0 0 0 0 0 0
Bit 7 – SHORTPACKETIC Short Packet Interrupt Clear
Bit 6 – RXST
ALLDIC Received STALLed Interrupt Clear
Bit 5 – OVERFIC Overflow Interrupt Clear
Bit 4 – NAKEDIC NAKed Interrupt Clear
Bit 2 – TXSTPIC Transmitted SETUP Interrupt Clear
Bit 1 – TXOUTIC Transmitted OUT Data Interrupt Clear
Bit 0 – RXINIC Received IN Data Interrupt Clear
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 890