Datasheet

Value Description

Set when an error occurs on the current bank of the pipe. This triggers an interrupt if the

USBHS_HSTPIPIMR.PERRE bit is set. Refer to the USBHS_HSTPIPERRx register to determine the

source of the error

Bit 2 – UNDERFI Underflow Interrupt

This bit is set, for an isochronous and interrupt IN/OUT pipe, when an error flow occurs. This triggers an interrupt if

UNDERFIE = 1.

This bit is set, for an isochronous or interrupt OUT pipe, when a transaction underflow occurs in the current pipe (the

pipe cannot send the OUT data packet in time because the current bank is not ready). A zero-length-packet (ZLP) is

sent instead.

This bit is set, for an isochronous or interrupt IN pipe, when a transaction flow error occurs in the current pipe, i.e, the

current bank of the pipe is not free while a new IN USB packet is received. This packet is not stored in the bank. For

an interrupt pipe, the overflowed packet is ACKed to comply with the USB standard.

This bit is cleared when USBHS_HSTPIPICR.UNDERFIEC = 1.

Bit 1 – TXOUTI

Transmitted OUT Data Interrupt

Value Description

Cleared when USBHS_HSTPIPICR.TXOUTIC = 1.

Set when the current OUT bank is free and can be filled. This triggers an interrupt if

USBHS_HSTPIPIMR.TXOUTE = 1.

Bit 0 – RXINI Received IN Data Interrupt

Value Description

Cleared when USBHS_HSTPIPICR.RXINIC = 1.

Set when a new USB message is stored in the current bank of the pipe. This triggers an interrupt if the

USBHS_HSTPIPIMR.RXINE bit = 1.

SAM E70/S70/V70/V71 Family

USB High-Speed Interface (USBHS)

echnology Inc.

Datasheet

DS60001527D-page 886