Datasheet

Value Description
1
Set when an error occurs on the current bank of the pipe. This triggers an interrupt if the
USBHS_HSTPIPIMR.PERRE bit is set. Refer to the USBHS_HSTPIPERRx register to determine the
source of the error
.
Bit 2 – TXSTPI T
ransmitted SETUP Interrupt
Value Description
0
Cleared when USBHS_HSTPIPICR.TXSTPIC = 1.
1
Set, for control pipes, when the current SETUP bank is free and can be filled. This triggers an interrupt
if USBHS_HSTPIPIMR.TXSTPE = 1.
Bit 1 – TXOUTI T
ransmitted OUT Data Interrupt
Value Description
0
Cleared when USBHS_HSTPIPICR.TXOUTIC = 1.
1
Set when the current OUT bank is free and can be filled. This triggers an interrupt if
USBHS_HSTPIPIMR.TXOUTE = 1.
Bit 0 – RXINI Received IN Data Interrupt
Value Description
0
Cleared when USBHS_HSTPIPICR.RXINIC = 1.
1
Set when a new USB message is stored in the current bank of the pipe. This triggers an interrupt if
USBHS_HSTPIPIMR.RXINE = 1.
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 883