Datasheet
Value Name Description
0
BANK0 Current bank is bank0
1
BANK1 Current bank is bank1
2
BANK2 Current bank is bank2
3
Reserved
Bits 13:12 – NBUSYBK[1:0] Number of Busy Banks
This field indicates the number of busy banks.
For an OUT pipe, this field indicates the number of busy banks, filled by the user
, ready for OUT transfer. When all
banks are busy, this triggers a PEP_x interrupt if USBHS_HSTPIPIMRx.NBUSYBKE = 1.
For an IN pipe, this field indicates the number of busy banks filled by IN transaction from the Device. When all banks
are free, this triggers a PEP_x interrupt if USBHS_HSTPIPIMRx.NBUSYBKE = 1.
Value Name Description
0
0_BUSY 0 busy bank (all banks free)
1
1_BUSY 1 busy bank
2
2_BUSY 2 busy banks
3
3_BUSY 3 busy banks
Bits 9:8 – DTSEQ[1:0] Data T
oggle Sequence
This field indicates the data PID of the current bank.
For an OUT pipe, this field indicates the data toggle of the next packet that is to be sent.
For an IN pipe, this field indicates the data toggle of the received packet stored in the current bank.
Value Name Description
0
DATA0 Data0 toggle sequence
1
DATA1 Data1 toggle sequence
2
Reserved
3
Reserved
Bit 7 – SHORTPACKETI Short Packet Interrupt
Value Description
0
Cleared when USBHS_HSTPIPICR.SHORTPACKETIC = 1.
1
Set when a short packet is received by the host controller (packet length inferior to the PSIZE
programmed field).
Bit 6 – RXSTALLDI Received ST
ALLed Interrupt
This bit is set when a STALL handshake has been received on the current bank of the pipe. The pipe is automatically
frozen. This triggers an interrupt if USBHS_HSTPIPIMR.RXSTALLE = 1.
Value Description
0
Cleared when USBHS_HSTPIPICR.RXSTALLDIC = 1.
Bit 5 – OVERFI Overflow Interrupt
Value Description
0
Cleared when USBHS_HSTPIPICR.OVERFIC = 1.
1
Set when the current pipe has received more data than the maximum length of the current pipe. An
interrupt is triggered if USBHS_HSTPIPIMR.OVERFIE = 1.
Bit 4 – NAKEDI NAKed Interrupt
Value Description
0
Cleared when USBHS_HSTPIPICR.NAKEDIC = 1.
1
Set when a NAK has been received on the current bank of the pipe. This triggers an interrupt if
USBHS_HSTPIPIMR.NAKEDE = 1.
Bit 3 – PERRI Pipe Error Interrupt
Value Description
0
Cleared when the error source bit is cleared.
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 882