Datasheet

39.6.45 Host Pipe x Status Register (Control, Bulk Pipes)
Name: USBHS_HSTPIPISRx
Offset: 0x0530 + x*0x04 [x=0..9]
Reset: 0
Property: Read/Write
This register view is relevant only if PTYPE = 0x0 or 0x2 in ”Host Pipe x Configuration Register”.
Bit 31 30 29 28 27 26 25 24
PBYCT[10:4]
Access
Reset 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
PBYCT[3:0] CFGOK RWALL
Access
Reset 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
CURRBK[1:0] NBUSYBK[1:0] DTSEQ[1:0]
Access
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
SHORTPACKE
TI
RXSTALLDI OVERFI NAKEDI PERRI TXSTPI TXOUTI RXINI
Access
Reset 0 0 0 0 0 0 0 0
Bits 30:20 – PBYCT[10:0] Pipe Byte Count
This field contains the byte count of the FIFO.
For an OUT pipe, the field is incremented after each byte written by the user into the pipe and decremented after
each byte sent to the peripheral.
For an IN pipe, the field is incremented after each byte received from the peripheral and decremented after each byte
read by the user from the pipe.
This field may be updated 1 clock cycle after the R
WALL bit changes, so the user should not poll this field as an
interrupt bit.
Bit 18 – CFGOK Configuration OK Status
This bit is set/cleared when the USBHS_HSTPIPCFGx.ALLOC bit is set.
This bit is set if the pipe x number of banks (USBHS_HSTPIPCFGx.PBK) and size (USBHS_HSTPIPCFGx.PSIZE)
are correct compared to the maximal allowed number of banks and size for this pipe and to the maximal FIFO size
(i.e., the DPRAM size).
If this bit is cleared, the user should rewrite correct values for the PBK and PSIZE fields in the USBHS_HSTPIPCFGx
register.
Bit 16 – RWALL Read/Write Allowed
For an OUT pipe, this bit is set when the current bank is not full, i.e., the software can write further data into the FIFO.
For an IN pipe, this bit is set when the current bank is not empty, i.e., the software can read further data from the
FIFO.
This bit is cleared otherwise.
This bit is also cleared when the RXSTALLDI or the PERRI bit = 1.
Bits 15:14 – CURRBK[1:0] Current Bank
For non-control pipe, this field indicates the number of the current bank.
This field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll it as an interrupt bit.
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 881