Datasheet

39.6.26 Device Endpoint Interrupt Enable Register (Isochronous Endpoints)
Name: USBHS_DEVEPTIERx (ISOENPT)
Offset: 0x01F0 + x*0x04 [x=0..9]
Reset: 0
Property: Read/Write
This register view is relevant only if EPTYPE = 0x1 in ”Device Endpoint x Configuration Register”.
For additional information, see ”Device Endpoint x Mask Register (Isochronous Endpoints)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No ef
fect.
1: Clears the corresponding bit in USBHS_DEVEPTIMRx.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
RSTDTS EPDISHDMAS
Access
Reset 0 0
Bit 15 14 13 12 11 10 9 8
FIFOCONS KILLBKS NBUSYBKES ERRORTRANS
ES
DATAXES MDATAES
Access
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
SHORTPACKE
TES
CRCERRES OVERFES HBISOFLUSHE
S
HBISOINERRE
S
UNDERFES RXOUTES TXINES
Access
Reset 0 0 0 0 0 0 0 0
Bit 18 – RSTDTS Reset Data T
oggle Enable
Bit 16 – EPDISHDMAS Endpoint Interrupts Disable HDMA Request Enable
Bit 14 – FIFOCONS FIFO Control
Bit 13 – KILLBKS Kill IN Bank
Bit 12 – NBUSYBKES Number of Busy Banks Interrupt Enable
Bit 10 – ERRORTRANSES Transaction Error Interrupt Enable
Bit 9 – DATAXES DataX Interrupt Enable
Bit 8 – MDATAES MData Interrupt Enable
Bit 7 – SHORTPACKETES Short Packet Interrupt Enable
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 853