Datasheet

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DATA[15:0] Symbol Command Executed

0x0012 WP Write Page Flash

0x0022 WPL Write Page and Lock Flash

0x0032 EWP Erase Page and Write Page

0x0042 EWPL Erase Page and Write Page then Lock

0x0013 EA Erase All

0x0014 SLB Set Lock Bit

0x0024 CLB Clear Lock Bit

0x0015 GLB Get Lock Bit

0x0034 SGPB Set General Purpose NVM bit

0x0044 CGPB Clear General Purpose NVM bit

0x0025 GGPB Get General Purpose NVM bit

0x0054 SSE Set Security Bit

0x0035 GSE Get Security Bit

0x001F WRAM Write Memory

0x001E GVE Get Version

18.3.3 Entering Parallel Programming Mode

The following algorithm puts the device in Parallel Programming mode:

Apply the supplies as described in table Signal Description List.

2. If an external clock is available, apply it to XIN within the VDDCORE POR reset time-out period, as defined in

the section “Electrical Characteristics”.

3. Wait for the end of this reset period.

4. Start a read or write handshaking.

18.3.4 Programmer Handshaking

A handshake is defined for read and write operations. When the device is ready to start a new operation (RDY signal

set), the programmer starts the handshake by clearing the NCMD signal. The handshaking is completed once the

NCMD signal is high and RDY is high.

18.3.4.1 Write Handshaking

For details on the write handshaking sequence, refer to the following figure and table.

SAM E70/S70/V70/V71 Family

Fast Flash Programming Interface (FFPI)

echnology Inc.

Datasheet

DS60001527D-page 85