Datasheet

39.6.24 Device Endpoint Interrupt Disable Register (Isochronous Endpoints)
Name: USBHS_DEVEPTIDRx (ISOENPT)
Offset: 0x0220 + x*0x04 [x=0..9]
Reset: 0
Property: Read/Write
This register view is relevant only if EPTYPE = 0x1 in ”Device Endpoint x Configuration Register”.
For additional information, see ”Device Endpoint x Mask Register (Isochronous Endpoints)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No ef
fect.
1: Clears the corresponding bit in USBHS_DEVEPTIMRx.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
EPDISHDMAC
Access
Reset 0
Bit 15 14 13 12 11 10 9 8
FIFOCONC NBUSYBKEC ERRORTRANS
EC
DATAXEC MDATEC
Access
Reset 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
SHORTPACKE
TEC
CRCERREC OVERFEC HBISOFLUSHE
C
HBISOINERRE
C
UNDERFEC RXOUTEC TXINEC
Access
Reset 0 0 0 0 0 0 0 0
Bit 16 – EPDISHDMAC Endpoint Interrupts Disable HDMA Request Clear
Bit 14 – FIFOCONC FIFO Control Clear
Bit 12 – NBUSYBKEC
Number of Busy Banks Interrupt Clear
Bit 10 – ERRORTRANSEC Transaction Error Interrupt Clear
Bit 9 – DATAXEC DataX Interrupt Clear
Bit 8 – MDATEC MData Interrupt Clear
Bit 7 – SHORTPACKETEC Shortpacket Interrupt Clear
Bit 6 – CRCERREC CRC Error Interrupt Clear
Bit 5 – OVERFEC Overflow Interrupt Clear
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 849