Datasheet

Value Description
0
Cleared when USBHS_DEVEPTIDRx.SHORTPACKETEC = 1. This disables the Short Packet interrupt
(USBHS_DEVEPTISRx.SHOR
TPACKET).
1
Set when USBHS_DEVEPTIERx.SHORTPACKETES = 1. This enables the Short Packet interrupt
(USBHS_DEVEPTISRx.SHORTPACKET).
Bit 6 – CRCERRE CRC Error Interrupt
Value Description
0
Cleared when USBHS_DEVEPTIDRx.CRCERREC = 1. This disables the CRC Error interrupt
(USBHS_DEVEPTISRx.CRCERRI).
1
Set when USBHS_DEVEPTIERx.CRCERRES = 1. This enables the CRC Error interrupt
(USBHS_DEVEPTISRx.CRCERRI).
Bit 5 – OVERFE Overflow Interrupt
Value Description
0
Cleared when USBHS_DEVEPTIDRx.OVERFEC = 1. This disables the Overflow interrupt
(USBHS_DEVEPTISRx.OVERFI).
1
Set when USBHS_DEVEPTIERx.OVERFES = 1. This enables the Overflow interrupt
(USBHS_DEVEPTISRx.OVERFI).
Bit 4 – HBISOFLUSHE High Bandwidth Isochronous IN Flush Interrupt
Value Description
0
Cleared when the USBHS_DEVEPTIDRx.HBISOFLUSHEC bit disables the HBISOFLUSHI interrupt.
1
Set when USBHS_DEVEPTIERx.HBISOFLUSHES = 1. This enables the HBISOFLUSHI interrupt.
Bit 3 – HBISOINERRE High Bandwidth Isochronous IN Error Interrupt
Value Description
0
Cleared when the USBHS_DEVEPTIDRx.HBISOINERREC bit disables the HBISOINERRI interrupt.
1
Set when USBHS_DEVEPTIERx.HBISOINERRES = 1. This enables the HBISOINERRI interrupt.
Bit 2 – UNDERFE Underflow Interrupt
Value Description
0
Cleared when USBHS_DEVEPTIDRx.UNDERFEC = 1. This disables the Underflow interrupt
(USBHS_DEVEPTISRx.UNDERFI).
1
Set when USBHS_DEVEPTIERx.UNDERFES = 1. This enables the Underflow interrupt
(USBHS_DEVEPTISRx.UNDERFI).
Bit 1 – RXOUTE Received OUT Data Interrupt
Value Description
0
Cleared when USBHS_DEVEPTIDRx.RXOUTEC = 1. This disables the Received OUT Data interrupt
(USBHS_DEVEPTISRx.RXOUTI).
1
Set when USBHS_DEVEPTIERx.RXOUTES = 1. This enables the Received OUT Data interrupt
(USBHS_DEVEPTISRx.RXOUTI).
Bit 0 – TXINE T
ransmitted IN Data Interrupt
Value Description
0
Cleared when USBHS_DEVEPTIDRx.TXINEC = 1. This disables the Transmitted IN Data interrupt
(USBHS_DEVEPTISRx.TXINI).
1
Set when USBHS_DEVEPTIERx.TXINES = 1. This enables the Transmitted IN Data interrupt
(USBHS_DEVEPTISRx.TXINI).
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 846