Datasheet

In Ping-pong mode, if the interrupt is associated to a new system-bank packet (e.g. Bank1) and the current DMA
transfer is running on the previous packet (Bank0), then the previous-packet DMA transfer completes normally
, but
the new-packet DMA transfer does not start (not requested).
If the interrupt is not associated to a new system-bank packet (USBHS_DEVEPTISRx.NAKINI, NAKOUTI, etc.), then
the request cancellation may occur at any time and may immediately pause the current DMA transfer.
This may be used for example to identify erroneous packets, to prevent them from being transferred into a buffer, to
complete a DMA transfer by software after reception of a short packet, etc.
Bit 14 – FIFOCON FIFO Control
For control endpoints:
The FIFOCON and RWALL bits are irrelevant. Therefore, the software never uses them on these endpoints. When
read, their value is always 0.
For IN endpoints:
0: Cleared (by writing a one to the USBHS_DEVEPTIDRx.FIFOCONC bit) to send the FIFO data and to switch to the
next bank.
1: Set when the current bank is free, at the same time as USBHS_DEVEPTISRx.TXINI.
For OUT endpoints:
0: Cleared (by writing a one to the USBHS_DEVEPTIDRx.FIFOCONC bit) to free the current bank and to switch to
the next bank.
1: Set when the current bank is full, at the same time as USBHS_DEVEPTISRx.RXOUTI.
Bit 13 – KILLBK Kill IN Bank
This bit is set when the USBHS_DEVEPTIERx.KILLBKS bit is written to one. This kills the last written bank.
This bit is cleared when the bank is killed.
CAUTION
The bank is really cleared when the “kill packet” procedure is accepted by the USBHS core. This bit is
automatically cleared after the end of the procedure.
The bank is really killed: USBHS_DEVEPTISRx.NBUSYBK is decremented.
The bank is not cleared but sent (IN transfer): USBHS_DEVEPTISRx.NBUSYBK is decremented.
The bank is not cleared because it was empty
.
The user should wait for this bit to be cleared before trying to kill another packet.
This kill request is refused if at the same time an IN token is coming and the last bank is the current one being sent
on the USB line. If at least two banks are ready to be sent, there is no problem to kill a packet even if an IN token is
coming. Indeed, in this case, the current bank is sent (IN transfer) while the last bank is killed.
Bit 12 – NBUSYBKE Number of Busy Banks Interrupt
Value Description
0
Cleared when USBHS_DEVEPTIDRx.NBUSYBKEC = 0. This disables the Number of Busy Banks
interrupt (USBHS_DEVEPTISRx.NBUSYBK).
1
Set when the USBHS_DEVEPTIERx.NBUSYBKES = 1. This enables the Number of Busy Banks
interrupt (USBHS_DEVEPTISRx.NBUSYBK).
Bit 7 – SHORTPACKETE Short Packet Interrupt
If this bit is set for non-control IN endpoints, a short packet transmission is guaranteed upon ending a DMA transfer
,
thus signaling an end of isochronous frame or a bulk or interrupt end of transfer, provided that the End of DMA Buffer
Output Enable (END_B_EN) bit and the Automatic Switch (AUTOSW) = 1.
Value Description
0
Cleared when USBHS_DEVEPTIDRx.SHORTPACKETEC = 1. This disables the Short Packet interrupt
(USBHS_DEVEPTISRx.SHOR
TPACKET).
1
Set when USBHS_DEVEPTIERx.SHORTPACKETES = 1. This enables the Short Packet interrupt
(USBHS_DEVEPTISRx.SHORTPACKET).
Bit 6 – STALLEDE ST
ALLed Interrupt
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 842