Datasheet

39.6.17 Device Endpoint Interrupt Clear Register (Control, Bulk, Interrupt Endpoints)
Name: USBHS_DEVEPTICRx
Offset: 0x0160 + x*0x04 [x=0..9]
Reset: 0
Property: Read/Write
This register view is relevant only if EPTYPE = 0x0, 0x2, or 0x3 in the ”Device Endpoint x Configuration Register”.
For additional information, see ”Device Endpoint x Status Register (Control, Bulk, Interrupt Endpoints)”.
This register always reads as zero.
The following configuration values are valid for all listed bit names of this register:
0: No ef
fect.
1: Clears the corresponding bit in USBHS_DEVEPTISRx.
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
Access
Reset
Bit 7 6 5 4 3 2 1 0
SHORTPACKE
TC
STALLEDIC OVERFIC NAKINIC NAKOUTIC RXSTPIC RXOUTIC TXINIC
Access
Reset 0 0 0 0 0 0 0 0
Bit 7 – SHORTPACKETC Short Packet Interrupt Clear
Bit 6 – ST
ALLEDIC STALLed Interrupt Clear
Bit 5 – OVERFIC Overflow Interrupt Clear
Bit 4 – NAKINIC NAKed IN Interrupt Clear
Bit 3 – NAKOUTIC NAKed OUT Interrupt Clear
Bit 2 – RXSTPIC Received SETUP Interrupt Clear
Bit 1 – RXOUTIC Received OUT Data Interrupt Clear
Bit 0 – TXINIC Transmitted IN Data Interrupt Clear
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 837