Datasheet

For IN endpoints:

0: Cleared when TXINIC = 1. This acknowledges the interrupt, which has no ef

fect on the endpoint FIFO.

USBHS_DEVEPTISRx.TXINI shall always be cleared before clearing USBHS_DEVEPTIMRx.FIFOCON.

1: Set at the same time as USBHS_DEVEPTIMRx.FIFOCON when the current bank is free. This triggers a PEP_x

interrupt if TXINE = 1.

The user writes into the FIFO and clears the USBHS_DEVEPTIMRx.FIFOCON bit to allow the USBHS to send the

data. If the IN endpoint is composed of multiple banks, this also switches to the next bank. The

USBHS_DEVEPTISRx.TXINI and USBHS_DEVEPTIMRx.FIFOCON bits are set/cleared in accordance with the

status of the next bank.

This bit is inactive (cleared) for OUT endpoints.

SAM E70/S70/V70/V71 Family

USB High-Speed Interface (USBHS)

echnology Inc.

Datasheet

DS60001527D-page 836