Datasheet

Value Name Description
0
BANK0 Current bank is bank0
1
BANK1 Current bank is bank1
2
BANK2 Current bank is bank2
3
Reserved
Bits 13:12 – NBUSYBK[1:0] Number of Busy Banks
This field is set to indicate the number of busy banks:
For IN endpoints, it indicates the number of banks filled by the user and ready for IN transfer
. When all banks are
free, this triggers a PEP_x interrupt if NBUSYBKE = 1.
For OUT endpoints, it indicates the number of banks filled by OUT transactions from the host. When all banks are
busy, this triggers a PEP_x interrupt if NBUSYBKE = 1.
When the USBHS_DEVEPTIMRx.FIFOCON bit is cleared (by writing a one to the
USBHS_DEVEPTIMRx.FIFOCONC bit) to validate a new bank, this field is updated two or three clock cycles later to
calculate the address of the next bank.
A PEP_x interrupt is triggered if:
Value Name Description
0
0_BUSY 0 busy bank (all banks free)
1
1_BUSY 1 busy bank
2
2_BUSY 2 busy banks
3
3_BUSY 3 busy banks
• For IN endpoint, USBHS_DEVEPTIMRx.NBUSYBKE = 1 and all the banks are free.
• For OUT endpoint, USBHS_DEVEPTIMRx.NBUSYBKE = 1 and all the banks are busy
.
Bit 10 – ERRORTRANS High-bandwidth Isochronous OUT Endpoint T
ransaction Error Interrupt
This bit is set when a transaction error occurs during the current microframe (the data toggle sequencing is not
compliant with the USB 2.0 standard). This triggers a PEP_x interrupt if USBHS_DEVEPTIMRx.ERRORTRANSE =
1.
This bit is set as long as the current bank (CURRBK) belongs to the bad n-transactions (n = 1, 2 or 3) transferred
during the microframe. It is cleared by software by clearing (at least once) the USBHS_DEVEPTIMRx.FIFOCON bit
to switch to the bank that belongs to the next n-transactions (next microframe).
Bits 9:8 – DTSEQ[1:0] Data Toggle Sequence
This field is set to indicate the PID of the current bank:
For IN transfers, it indicates the data toggle sequence that should be used for the next packet to be sent. This is not
relative to the current bank.
For OUT transfers, this value indicates the last data toggle sequence received on the current bank.
By default, DTSEQ is 0b01, as if the last data toggle sequence was Data1, so the next sent or expected data toggle
sequence should be Data0.
For high-bandwidth isochronous endpoint, a PEP_x interrupt is triggered if:
Value Name Description
0
DATA0 Data0 toggle sequence
1
DATA1 Data1 toggle sequence
2
DATA2 Data2 toggle sequence (for high-bandwidth isochronous endpoint)
3
MDATA MData toggle sequence (for high-bandwidth isochronous endpoint)
• USBHS_DEVEPTIMRx.MDA
TAE = 1 and a MData packet has been received (DTSEQ =
MData and USBHS_DEVEPTISRx.RXOUTI = 1).
• USBHS_DEVEPTISRx.DATAXE = 1 and a Data0/1/2 packet has been received (DTSEQ =
Data0/1/2 and USBHS_DEVEPTISRx.RXOUTI = 1).
Bit 7 – SHORTPACKET Short Packet Interrupt
Value Description
0
Cleared when SHORTPACKETC = 1. This acknowledges the interrupt.
1
Set for non-control OUT endpoints, when a short packet has been received. This triggers a PEP_x
interrupt if USBHS_DEVEPTIMRx.SHOR
TPACKETE = 1.
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 834