Datasheet

39.6.16 Device Endpoint Interrupt Status Register (Isochronous Endpoints)
Name: USBHS_DEVEPTISRx (ISOENPT)
Offset: 0x0130 + x*0x04 [x=0..9]
Reset: 0
Property: Read/Write
This register view is relevant only if EPTYPE = 0x1 in the ”Device Endpoint x Configuration Register”.
Bit 31 30 29 28 27 26 25 24
BYCT[10:4]
Access
Reset 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
BYCT[3:0] CFGOK RWALL
Access
Reset 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
CURRBK[1:0] NBUSYBK[1:0] ERRORTRANS DTSEQ[1:0]
Access
Reset 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
SHORTPACKE
T
CRCERRI OVERFI HBISOFLUSHI HBISOINERRI UNDERFI RXOUTI TXINI
Access
Reset 0 0 0 0 0 0 0 0
Bits 30:20 – BYCT[10:0] Byte Count
This field is set with the byte count of the FIFO.
For IN endpoints, the field is incremented after each byte written by the software into the endpoint and decremented
after each byte sent to the host.
For OUT endpoints, the field is incremented after each byte received from the host and decremented after each byte
read by the software from the endpoint.
This field may be updated one clock cycle after the R
WALL bit changes, so the user should not poll this field as an
interrupt bit.
Bit 18 – CFGOK Configuration OK Status
This bit is updated when USBHS_DEVEPTCFGx.ALLOC = 1.
This bit is set if the endpoint x number of banks (USBHS_DEVEPTCFGx.EPBK) and size
(USBHS_DEVEPTCFGx.EPSIZE) are correct compared to the maximal allowed number of banks and size for this
endpoint and to the maximal FIFO size (i.e., the DPRAM size).
If this bit is cleared, the user should rewrite correct values to the USBHS_DEVEPTCFGx.EPBK and
USBHS_DEVEPTCFGx.EPSIZE fields.
Bit 16 – RWALL Read/Write Allowed
This bit is set for IN endpoints when the current bank is not full, i.e., the user can write further data into the FIFO.
This bit is set for OUT endpoints when the current bank is not empty, i.e., the user can read further data from the
FIFO.
This bit is never set in case of error.
This bit is cleared otherwise.
Bits 15:14 – CURRBK[1:0] Current Bank
This field is used to indicate the current bank. It may be updated one clock cycle after the RWALL bit changes, so the
user should not poll this field as an interrupt bit.
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 833