Datasheet

Bit 5 – OVERFI Overflow Interrupt
For all endpoint types, an overflow can occur during the OUT stage if the host attempts to write into a bank that is too
small for the packet. The packet is acknowledged and the USBHS_DEVEPTISRx.RXOUTI bit is set as if no overflow
had occurred. The bank is filled with all the first bytes of the packet that fit in.
Value Description
0
Cleared when the OVERFIC bit is written to one. This acknowledges the interrupt.
1
Set when an overflow error occurs. This triggers a PEP_x interrupt if OVERFE = 1.
Bit 4 – NAKINI NAKed IN Interrupt
Value Description
0
Cleared when NAKINIC = 1. This acknowledges the interrupt.
1
Set when a NAK handshake has been sent in response to an IN request from the host. This triggers a
PEP_x interrupt if NAKINE = 1.
Bit 3 – NAKOUTI NAKed OUT Interrupt
Value Description
0
Cleared when NAKOUTIC = 1. This acknowledges the interrupt.
1
Set when a NAK handshake has been sent in response to an OUT request from the host. This triggers
a PEP_x interrupt if NAKOUTE = 1.
Bit 2 – RXSTPI Received SETUP Interrupt
This bit is set, for control endpoints, to signal that the current bank contains a new valid SETUP packet. This triggers
a PEP_x interrupt if RXSTPE = 1.
It is cleared by writing a one to the RXSTPIC bit. This acknowledges the interrupt and frees the bank.
This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints.
Bit 1 – RXOUTI Received OUT Data Interrupt
For control endpoints:
0: Cleared by writing a one to the RXOUTIC bit. This acknowledges the interrupt and frees the bank.
1: Set when the current bank contains a bulk OUT packet (data or status stage). This triggers a PEP_x interrupt if
USBHS_DEVEPTIMRx.RXOUTE = 1.
For bulk and interrupt OUT endpoints:
0: Cleared by writing a one to the RXOUTIC bit. This acknowledges the interrupt, which has no ef
fect on the endpoint
FIFO. USBHS_DEVEPTISRx.RXOUTI shall always be cleared before clearing USBHS_DEVEPTIMRx.FIFOCON.
1: Set at the same time as USBHS_DEVEPTIMRx.FIFOCON when the current bank is full. This triggers a PEP_x
interrupt if USBHS_DEVEPTIMRx.RXOUTE = 1.
The user reads from the FIFO and clears the USBHS_DEVEPTIMRx.FIFOCON bit to free the bank. If the OUT
endpoint is composed of multiple banks, this also switches to the next bank. The USBHS_DEVEPTISRx.RXOUTI
and USBHS_DEVEPTIMRx.FIFOCON bits are set/cleared in accordance with the status of the next bank.
This bit is inactive (cleared) for bulk and interrupt IN endpoints.
Bit 0 – TXINI Transmitted IN Data Interrupt
For control endpoints:
0: Cleared when TXINIC = 1. This acknowledges the interrupt and sends the packet.
1: Set when the current bank is ready to accept a new IN packet. This triggers a PEP_x interrupt if TXINE = 1.
For bulk and interrupt IN endpoints:
0: Cleared when TXINIC = 1. This acknowledges the interrupt, which has no effect on the endpoint FIFO.
USBHS_DEVEPTISRx.TXINI shall always be cleared before clearing USBHS_DEVEPTIMRx.FIFOCON.
1: Set at the same time as USBHS_DEVEPTIMRx.FIFOCON when the current bank is free. This triggers a PEP_x
interrupt if TXINE = 1.
The user writes into the FIFO and clears the USBHS_DEVEPTIMRx.FIFOCON bit to allow the USBHS to send the
data. If the IN endpoint is composed of multiple banks, this also switches to the next bank. The
USBHS_DEVEPTISRx.TXINI and USBHS_DEVEPTIMRx.FIFOCON bits are set/cleared in accordance with the
status of the next bank.
This bit is inactive (cleared) for bulk and interrupt OUT endpoints.
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 832