Datasheet

39.6.14 Device Endpoint x Configuration Register
Name: USBHS_DEVEPTCFGx
Offset: 0x0100 + x*0x04 [x=0..9]
Reset: 0
Property: Read/Write
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
Access
Reset
Bit 15 14 13 12 11 10 9 8
NBTRANS[1:0] EPTYPE[1:0] AUTOSW EPDIR
Access
Reset 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
EPSIZE[2:0] EPBK[1:0] ALLOC
Access
Reset 0 0 0 0 0 0
Bits 14:13 – NBTRANS[1:0] Number of transactions per microframe for isochronous endpoint
This field should be written with the number of transactions per microframe to perform high-bandwidth isochronous
transfer
.
It can be written only for endpoints that have this capability (see USBHS_FEATURES.ENHBISOx bit). Otherwise, this
field is 0.
This field is irrelevant for non-isochronous endpoints.
Value Name Description
0
0_TRANS Reserved to endpoint that does not have the high-bandwidth isochronous capability.
1
1_TRANS Default value: one transaction per microframe.
2
2_TRANS Two transactions per microframe. This endpoint should be configured as double-bank.
3
3_TRANS Three transactions per microframe. This endpoint should be configured as triple-bank.
Bits 12:11 – EPTYPE[1:0] Endpoint T
ype
This field should be written to select the endpoint type:
This field is cleared upon receiving a USB reset.
Value Name Description
0
CTRL Control
1
ISO Isochronous
2
BLK Bulk
3
INTRPT Interrupt
Bit 9 – AUTOSW Automatic Switch
This bit is cleared upon receiving a USB reset.
Value Description
0
The automatic bank switching is disabled.
1
The automatic bank switching is enabled.
Bit 8 – EPDIR Endpoint Direction
This bit is cleared upon receiving a USB reset.
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 828