Datasheet

39.6.5 Device General Control Register
Name: USBHS_DEVCTRL
Offset: 0x0000
Reset: 0x00000100
Property: Read/Write
Bit 31 30 29 28 27 26 25 24
Access
Reset
Bit 23 22 21 20 19 18 17 16
OPMODE2
Access
Reset 0
Bit 15 14 13 12 11 10 9 8
TSTPCKT TSTK TSTJ LS SPDCONF[1:0] RMWKUP DETACH
Access
Reset 0 0 0 0 0 0 0 1
Bit 7 6 5 4 3 2 1 0
ADDEN UADD[6:0]
Access
Reset 0 0 0 0 0 0 0 0
Bit 16 – OPMODE2 Specific Operational mode
Value Description
0
The UTMI transceiver is in Normal operating mode.
1
The UTMI transceiver is in the “Disable bit stuffing and NRZI encoding” operational mode for test
purposes.
Bit 15 – TSTPCKT T
est packet mode
Value Description
0
The UTMI transceiver is in Normal operating mode.
1
The UTMI transceiver generates test packets for test purposes.
Bit 14 – TSTK T
est mode K
Value Description
0
The UTMI transceiver is in Normal operating mode.
1
The UTMI transceiver generates high-speed K state for test purposes.
Bit 13 – TSTJ T
est mode J
Value Description
0
The UTMI transceiver is in Normal operating mode.
1
The UTMI transceiver generates high-speed J state for test purposes.
Bit 12 – LS Low-Speed Mode Force
This bit can be written even if USBHS_CTRL.USBE = 0 or USBHS_CTRL.FRZCLK = 1. Disabling the USBHS (by
writing a zero to the USBHS_CTRL.USBE bit) does not reset this bit.
Value Description
0
The Full-speed mode is active.
1
The Low-speed mode is active.
SAM E70/S70/V70/V71 Family
USB High-Speed Interface (USBHS)
© 2019 Microchip T
echnology Inc.
Datasheet
DS60001527D-page 817